\doxysection{HSEM\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_h_s_e_m___type_def}{}\label{struct_h_s_e_m___type_def}\index{HSEM\_TypeDef@{HSEM\_TypeDef}}


HW Semaphore HSEM.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_h_s_e_m___type_def_ab568605bc809dfe668847dd7bc89dc8a}{R}} \mbox{[}32\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_h_s_e_m___type_def_adef549dba3b342ce45e57ae1a5c330d0}{RLR}} \mbox{[}32\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_h_s_e_m___type_def_a69c1de4348244e1e36072b01bbcd0f75}{C1\+IER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_h_s_e_m___type_def_adbebccb559027a2b858a3c85cc0b224a}{C1\+ICR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_h_s_e_m___type_def_a69174dfb50f2b0b06ed8ac999982f3b9}{C1\+ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_h_s_e_m___type_def_a93c90ca6f26ab1e3ae5d027761d41537}{C1\+MISR}}
\item 
\Hypertarget{struct_h_s_e_m___type_def_ab6dd340222147610b4c231bbaa29f01d}\label{struct_h_s_e_m___type_def_ab6dd340222147610b4c231bbaa29f01d} 
uint32\+\_\+t {\bfseries Reserved} \mbox{[}12\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_h_s_e_m___type_def_ab207840b89471c745e4302e2970fed13}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_h_s_e_m___type_def_a41f7be8cb97e115cde34582815fac8c0}{KEYR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
HW Semaphore HSEM. 

\label{doc-variable-members}
\Hypertarget{struct_h_s_e_m___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_h_s_e_m___type_def_adbebccb559027a2b858a3c85cc0b224a}\index{HSEM\_TypeDef@{HSEM\_TypeDef}!C1ICR@{C1ICR}}
\index{C1ICR@{C1ICR}!HSEM\_TypeDef@{HSEM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{C1ICR}{C1ICR}}
{\footnotesize\ttfamily \label{struct_h_s_e_m___type_def_adbebccb559027a2b858a3c85cc0b224a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t HSEM\+\_\+\+Type\+Def\+::\+C1\+ICR}

HSEM Interrupt clear register , Address offset\+: 104h \Hypertarget{struct_h_s_e_m___type_def_a69c1de4348244e1e36072b01bbcd0f75}\index{HSEM\_TypeDef@{HSEM\_TypeDef}!C1IER@{C1IER}}
\index{C1IER@{C1IER}!HSEM\_TypeDef@{HSEM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{C1IER}{C1IER}}
{\footnotesize\ttfamily \label{struct_h_s_e_m___type_def_a69c1de4348244e1e36072b01bbcd0f75} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t HSEM\+\_\+\+Type\+Def\+::\+C1\+IER}

HSEM Interrupt enable register , Address offset\+: 100h \Hypertarget{struct_h_s_e_m___type_def_a69174dfb50f2b0b06ed8ac999982f3b9}\index{HSEM\_TypeDef@{HSEM\_TypeDef}!C1ISR@{C1ISR}}
\index{C1ISR@{C1ISR}!HSEM\_TypeDef@{HSEM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{C1ISR}{C1ISR}}
{\footnotesize\ttfamily \label{struct_h_s_e_m___type_def_a69174dfb50f2b0b06ed8ac999982f3b9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t HSEM\+\_\+\+Type\+Def\+::\+C1\+ISR}

HSEM Interrupt Status register , Address offset\+: 108h \Hypertarget{struct_h_s_e_m___type_def_a93c90ca6f26ab1e3ae5d027761d41537}\index{HSEM\_TypeDef@{HSEM\_TypeDef}!C1MISR@{C1MISR}}
\index{C1MISR@{C1MISR}!HSEM\_TypeDef@{HSEM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{C1MISR}{C1MISR}}
{\footnotesize\ttfamily \label{struct_h_s_e_m___type_def_a93c90ca6f26ab1e3ae5d027761d41537} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t HSEM\+\_\+\+Type\+Def\+::\+C1\+MISR}

HSEM Interrupt Masked Status register , Address offset\+: 10Ch \Hypertarget{struct_h_s_e_m___type_def_ab207840b89471c745e4302e2970fed13}\index{HSEM\_TypeDef@{HSEM\_TypeDef}!CR@{CR}}
\index{CR@{CR}!HSEM\_TypeDef@{HSEM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_h_s_e_m___type_def_ab207840b89471c745e4302e2970fed13} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t HSEM\+\_\+\+Type\+Def\+::\+CR}

HSEM Semaphore clear register , Address offset\+: 140h \Hypertarget{struct_h_s_e_m___type_def_a41f7be8cb97e115cde34582815fac8c0}\index{HSEM\_TypeDef@{HSEM\_TypeDef}!KEYR@{KEYR}}
\index{KEYR@{KEYR}!HSEM\_TypeDef@{HSEM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{KEYR}{KEYR}}
{\footnotesize\ttfamily \label{struct_h_s_e_m___type_def_a41f7be8cb97e115cde34582815fac8c0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t HSEM\+\_\+\+Type\+Def\+::\+KEYR}

HSEM Semaphore clear key register , Address offset\+: 144h \Hypertarget{struct_h_s_e_m___type_def_ab568605bc809dfe668847dd7bc89dc8a}\index{HSEM\_TypeDef@{HSEM\_TypeDef}!R@{R}}
\index{R@{R}!HSEM\_TypeDef@{HSEM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{R}{R}}
{\footnotesize\ttfamily \label{struct_h_s_e_m___type_def_ab568605bc809dfe668847dd7bc89dc8a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t HSEM\+\_\+\+Type\+Def\+::R\mbox{[}32\mbox{]}}

2-\/step write lock and read back registers, Address offset\+: 00h-\/7\+Ch \Hypertarget{struct_h_s_e_m___type_def_adef549dba3b342ce45e57ae1a5c330d0}\index{HSEM\_TypeDef@{HSEM\_TypeDef}!RLR@{RLR}}
\index{RLR@{RLR}!HSEM\_TypeDef@{HSEM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RLR}{RLR}}
{\footnotesize\ttfamily \label{struct_h_s_e_m___type_def_adef549dba3b342ce45e57ae1a5c330d0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t HSEM\+\_\+\+Type\+Def\+::\+RLR\mbox{[}32\mbox{]}}

1-\/step read lock registers, Address offset\+: 80h-\/\+FCh 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
